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INTEGRATED CIRCUITS
DATA SHEET
UAA2077AM Image rejecting front-end for DECT applications
Product specification Supersedes data of 1995 Feb 16 File under Integrated Circuits, IC17 1996 Jul 04
Philips Semiconductors
Product specification
Image rejecting front-end for DECT applications
FEATURES * Low-noise, wide dynamic range amplifier * Very low noise figure * Dual balanced mixer for over 25 dB on-chip image rejection * IF I/Q combiner at 110 MHz * On-chip quadrature network * RX fast on/off power-down mode * Shrink small outline packaging * Very small application (no image filter). APPLICATIONS * 1800 MHz front-end for DECT hand-portable equipment * Compact digital mobile communication equipment * TDMA receivers. GENERAL DESCRIPTION UAA2077AM contains a high frequency low noise receiver front-end intended to be used in DECT mobile telephones. Designed in an advanced BiCMOS process it combines high performance with low power consumption and a high degree of integration, thus reducing external component costs and total front-end size. The main advantage of the UAA2077AM is its ability to provide over 25 dB of image rejection. Consequently, the image filter between the LNA and the mixer is suppressed. QUICK REFERENCE DATA SYMBOL VCC ICC(RX) ICC(PD) Tamb PARAMETER supply voltage receive supply current supply current in power-down operating ambient temperature CONDITIONS Tamb = 0 to +70 C over full temperature range MIN. 3.15 3.6 21.5 - -30
UAA2077AM
Image rejection is achieved in the internal architecture by two RF mixers in quadrature and two all-pass filters in I and Q IF channels that phase shift the IF by 45 and 135 respectively. The two phase shifted IFs are recombined and buffered to furnish the IF output signal. For instance, signals presented at the RF input at LO + IF frequency are rejected through this signal processing while signals at LO - IF frequency can form the IF signal. An internal switch enables the upper or lower image frequency to be rejected. The receiver section consists of a low-noise amplifier that drives a quadrature mixer pair. The IF amplifier has on-chip 45 and 135 phase shifting and a combining network for image rejection. The IF driver has differential open-collector type outputs. The LO part consists of an internal all-pass type phase shifter to provide quadrature LO signals to the receive mixers.The centre frequency of the phase shifter is adjustable for maximum image rejection in a given band. The all-pass filters outputs are buffered before being fed to the receive mixers. All RF and IF inputs or outputs are balanced. Two pins RXON and SXON are used to control the different power-down modes. A special mode of operation called synthesizer-on mode (SX mode), controlled by pin SXON can be used to minimize the LO pulling when the receiver is turned on. When SXON is HIGH, all internal buffers on the LO path are turned on. Pin SBS allows a selection of whether to reject the upper or lower image frequency. Special care has been taken for fast power-up switching.
TYP. 4.0 4.0 26.5 0.2 +25
MAX. 5.3 5.3 33.5 50 +85
UNIT V V mA A C
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME UAA2077AM SSOP20 DESCRIPTION plastic shrink small outline package; 20 leads; body width 4.4 mm VERSION SOT266-1
1996 Jul 04
2
Philips Semiconductors
Product specification
Image rejecting front-end for DECT applications
BLOCK DIAGRAM
UAA2077AM
handbook, full pagewidth
n.c. 4
n.c. 7
SXON RXON 9 12
SBS
UAA2077AM
+45o
11
VCCLNA
3 17 IFA
RFINA RFINB
5 6 LNA low-noise amplifier +135o IF COMBINER 18 8
IFB
LNAGND
RECEIVE SECTION
VCCLO 15
LOCAL OSCILLATOR SECTION
10 QUADRATURE PHASE SHIFTER
VQUADLO
LOGND
16 14 LOINA 13
MBH154
LOINB
Fig.1 Block diagram.
1996 Jul 04
3
Philips Semiconductors
Product specification
Image rejecting front-end for DECT applications
PINNING SYMBOL n.c. n.c. VCCLNA n.c. RFINA RFINB n.c. LNAGND SXON VQUADLO SBS RXON LOINB LOINA VCCLO LOGND IFA IFB n.c. n.c. PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DESCRIPTION not connected not connected supply voltage for LNA and IF parts not connected RF input A (balanced) RF input B (balanced) not connected ground for LNA and IF parts SX mode enable (see Table 1) input voltage for LO quadrature trimming sideband selection RX mode enable (see Table 1) LO input B (balanced) LO input A (balanced) supply voltage for LO parts ground for LO parts IF output A (balanced) IF output B (balanced) not connected not connected
n.c. 7 LNAGND 8 SXON 9 VQUADLO 10
MBH151
UAA2077AM
handbook, halfpage
n.c. 1 n.c. 2 VCCLNA 3 n.c. 4 RFINA 5
20 n.c. 19 n.c. 18 IFB 17 IFA 16 LOGND
UAA2077AM
RFINB 6 15 VCCLO 14 LOINA 13 LOINB 12 RXON 11 SBS
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION Receive section The circuit contains a low-noise amplifier followed by two high dynamic range mixers. These mixers are of the Gilbert-cell type, the whole internal architecture is fully differential. The local oscillator, shifted in phase to 45 and 135, mixes the amplified RF to create I and Q channels. The two I and Q channels are buffered, phase shifted by 45 and 135 respectively, amplified and recombined internally to realize the image rejection. Pin SBS allows sideband selection: * fLO > fRF (SBS = 1) * fLO < fRF (SBS = 0). where fRF is the frequency of the wanted signal.
Balanced signal interfaces are used for minimizing crosstalk due to package parasitics. The IF output is differential and of the open-collector type. Typical application will load the output with a differential 1 k load; for example, a 1 k resistor load at each IF output, plus a differential 2 k load consisting of the input impedance of the IF filter or the input impedance of the matching network for the IF filter. The power gain refers to the available power on this 2 k load. The path to VCC for the DC current should be achieved via tuning inductors. The output voltage is limited to VCC + 3Vbe or 3 diode forward voltage drops. Fast switching, on/off, of the receive section is controlled by the hardware input RXON.
1996 Jul 04
4
Philips Semiconductors
Product specification
Image rejecting front-end for DECT applications
UAA2077AM
handbook, full pagewidth
SBS IF amplifier +45o
VCCLNA
MIXER
IFA RFINA RFINB LNA LNAGND IF amplifier +135o
MBH152
MIXER
IF COMBINER IFB
LOIN
RXON
Fig.3 Block diagram, receive section.
Local oscillator section The local oscillator (LO) input directly drives the two internal all-pass networks to provide quadrature LO to the receive mixers. The centre frequency of the receive band is adjustable by the voltage on pin VQUADLO. This should be achieved by connecting a resistor between VQUADLO and VCC. Over 25 dB of image rejection can be obtained by an optimum resistor value. A synthesizer-on (SX) mode is used to power-up the LO input buffers, thus minimizing the pulling effect on the external VCO when entering receive mode. This mode is active when SXON = 1. There are no internal biassing components attached to the pins LOINA and LOINB. These pins are connected by capacitors to the internal phase shifting network. Fig.4 Block diagram, LO section.
handbook, halfpage
to RX
VCCLO
VQUADLO
QUAD
LOGND
MBH153
LOINA
LOINB
1996 Jul 04
5
Philips Semiconductors
Product specification
Image rejecting front-end for DECT applications
Table 1 Control of power status EXTERNAL PIN LEVEL
UAA2077AM
CIRCUIT MODE OF OPERATION RXON LOW HIGH LOW SXON LOW X HIGH power-down mode RX mode (receive and LO sections on) SX mode (only LO section on)
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC GND Pl(max) Tj(max) Pmax Tstg supply voltage maximum power input maximum operating junction temperature maximum power dissipation IC storage temperature PARAMETER - - - - -65 difference in ground supply voltage applied between LOGND and LNAGND - MIN. 9 0.6 20 150 250 +150 MAX. V V dBm C mW C UNIT
THERMAL CHARACTERISTICS SYMBOL Rth j-a HANDLING Every pin withstands the ESD test in accordance with "MIL-STD-883C Class 2 (method 3015.5)". DC CHARACTERISTICS VCC = 4.0 V; Tamb = 25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT PARAMETER thermal resistance from junction to ambient in free air VALUE 120 UNIT K/W
Pins VCCLNA and VCCLO VCC ICC(RX) ICC(PD) ICC(SX) Vth VIH VIL IIH IIL supply voltage supply current in RX mode supply current in power-down mode supply current in SX mode Tamb = 0 to +70 C 3.15 21.5 - 3 - 0.7VCC -0.3 pin at VCC - 0.4 V pin at 0.4 V -1 -1 4.0 4.0 26.5 0.2 5 5.3 5.3 33.5 50 7 - VCC +0.8 +1 +1 V V mA A mA over full temperature range 3.6
Pins RXON, SXON and SBS CMOS threshold voltage HIGH level input voltage LOW level input voltage HIGH level static input current LOW level static input current note 1 1.25 - - - - V V V A A
1996 Jul 04
6
Philips Semiconductors
Product specification
Image rejecting front-end for DECT applications
SYMBOL PARAMETER CONDITIONS - - MIN.
UAA2077AM
TYP. - -
MAX.
UNIT
Pins RFINA and RFINB VI IO Note 1. The referenced inputs should be connected to a valid CMOS input level. AC CHARACTERISTICS VCC = 4.0 V; Tamb = -30 to +85 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS - MIN. TYP. - MAX. UNIT DC input voltage level receive section on 2.0 V
Pins IFA and IFB DC output current receive section on 2.5 mA
Receive section (receive section enabled) RiRX RF input resistance (real part of the parallel input impedance) RF input capacitance (imaginary part of the parallel input impedance) RF input frequency return loss on matched RF input conversion power gain balanced; note 1 differential RF inputs to differential IF outputs loaded to 1 k differential note 2 balanced; at 1890 MHz 60
CiRX
balanced; at 1890 MHz
-
1
-
pF
fiRX RLiRX GCP
1880 11 17
- 15 20
1900 - 23
MHz dB dB
Grip G/T CP1RX DES3
gain ripple as a function of RF frequency
- -20 -40 -26 -
0.2 0 -30 -23 -30
- +10 -20 - -
dB mdB/C mdB/C dBm dBm
gain variation with temperature Tamb = -30 to +25 C; note 2 Tamb = +25 to +85 C; note 2 1 dB compression point 3 dB desensitisation point differential RF inputs to differential IF outputs; note 1 interferer frequency offset: 3 MHz; differential RF inputs to differential IF outputs; note 1
interferer frequency offset: - 20 MHz; differential RF inputs to differential IF outputs; note 1 IP2DRX IP3RX NFRX 2nd order intercept point 3rd order intercept point overall noise figure differential RF inputs to differential IF outputs; note 2 differential RF inputs to differential IF outputs; note 2 differential RF inputs to differential IF outputs; notes 2 and 3 15 -23 -
-28
-
dBm
30 -17 4.3
- - 5.0
dBm dBm dB
1996 Jul 04
7
Philips Semiconductors
Product specification
Image rejecting front-end for DECT applications
SYMBOL ZLRX RLoRX foRX IR PARAMETER typical application IF output load impedance return loss on matched IF output IF frequency rejection of image frequency fLO < fRF; fIF = 110 MHz; note 4 CONDITIONS balanced balanced; note 1 - 11 - 26 MIN. 1 15 110 32 - 40 TYP.
UAA2077AM
MAX. - - - -
UNIT k dB MHz dB
Local oscillator section (receive section enabled) fiLO RiLO LO input frequency LO input resistance (real part of the parallel input impedance) LO input capacitance (imaginary part of the parallel input impedance) return loss on matched LO input (including power-down mode) return loss variation ratio between SX and RX modes LO input power level reverse isolation LOIN to RFIN at LO frequency; note 2 balanced; at 1780 MHz 1770 - 2010 - MHz
CiLO
balanced; at 1780 MHz
-
2
-
pF
RLiLO
note 1
9
12
-
dB
RLiLO PiLO RILO Timing tstart Notes
linear S11 variation; note 1
- -6 40
5 -3 -
- +3 -
mU dBm dB
start-up time of each block
1
5
20
s
1. Measured and guaranteed only on UAA2077AM demonstration board at Tamb = 25 C. 2. Measured and guaranteed only on UAA2077AM demonstration board. 3. This value includes printed-circuit board and balun losses. 4. Measured and guaranteed only on UAA2077AM demonstration board at Tamb = 25 C. VQUADLO open-circuit.
1996 Jul 04
8
Philips Semiconductors
Product specification
Image rejecting front-end for DECT applications
INTERNAL PIN CONFIGURATION SYMBOL VCCLNA PIN 3 DC VOLTAGE (V) 4.0
VCC
UAA2077AM
EQUIVALENT CIRCUIT
RFINA
5
2.0
5
6
RFINB
6
2.0
GND
MGG090
LNAGND SXON
8 9
0 -
VCC
SBS
11
-
9, 11,12
GND
RXON
12
-
VCC
MGG088
LOINB
13
-
13,14
LOINA
14
-
GND
MGG089
VCCLO
15
4.0
1996 Jul 04
9
Philips Semiconductors
Product specification
Image rejecting front-end for DECT applications
DC VOLTAGE (V) 0
VCC
UAA2077AM
SYMBOL LOGND
PIN 16
EQUIVALENT CIRCUIT
IFA
17
2.5
17
18
GND
IFB
18
2.5
GND
MGG091
1996 Jul 04
10
handbook, full pagewidth
1996 Jul 04
1 2 4V L6 5.6 nH C6 8.2 pF C1 RFIN 1880 to1900 MHz C2 1.2 pF L1 5.6 nH 8.2 pF C3 8.2 pF C14 1.2 pF L15 6.8 nH C5 82 pF 3 4 5 18 17 16 R6 1200 4V R7 1200 L11 220 nH L12 220 nH C22 IFA 120 pF C23 6.8 pF C24 IFB 120 nH L13 IF 110 MHz C25 22 pF L14 120 nH 4V 9 VQUADLO SXON 2 C8 8.2 pF R4 560 k 10 C30 8.2 pF C31 82 pF 2 C7 8.2 pF R3 560 k 12 11 C19 8.2 pF C20 1.8 pF 3.3 nH L9 C29 8.2 pF C21 1.8 pF C27 8.2 pF RXON 2 C9 8.2 pF R5 560 k 3.3 nH L10 C28 1 nF 20 19 6.8 pF 22 pF C26
APPLICATION INFORMATION
Philips Semiconductors
Image rejecting front-end for DECT applications
UAA2077AM
6 7 8 15 14 13
11
1
SBS
1
1
LOIN 1770 to 1790 MHz 4V
MGC631 - 1
UAA2077AM
Product specification
Figure 5 illustrates the electrical diagram of the UAA2077AM Philips demonstration board for DECT applications. All matching is to 50 for measurement purposes. Different values will be used in a real application.
Fig.5 Application diagram.
Philips Semiconductors
Product specification
Image rejecting front-end for DECT applications
PACKAGE OUTLINE SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm
UAA2077AM
SOT266-1
D
E
A X
c y HE vM A
Z
20
11
Q A2 pin 1 index A1 (A 3) Lp L A
1
e bp
10
detail X wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.15 0 A2 1.4 1.2 A3 0.25 bp 0.32 0.20 c 0.20 0.13 D (1) 6.6 6.4 E (1) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.45 Q 0.65 0.45 v 0.2 w 0.13 y 0.1 Z (1) 0.48 0.18 10 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT266-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 90-04-05 95-02-25
1996 Jul 04
12
Philips Semiconductors
Product specification
Image rejecting front-end for DECT applications
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
UAA2077AM
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Jul 04
13
Philips Semiconductors
Product specification
Image rejecting front-end for DECT applications
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
UAA2077AM
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 Jul 04
14
Philips Semiconductors
Product specification
Image rejecting front-end for DECT applications
NOTES
UAA2077AM
1996 Jul 04
15
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com/ps/ (1) UAA2077AM_4 June 26, 1996 11:51 am SCA50
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands
647021/1200/04/pp16 Date of release: 1996 Jul 04 Document order number: 9397 750 00919

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